1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, vertical transistors, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a simplistic depiction of an illustrative prior art vertical transistor device 10. In general, the vertical transistor 10 comprises a generally vertically oriented channel semiconductor structure 12A that extends upward from a front surface 12S of a semiconductor substrate 12. The semiconductor structure 12A may have a variety of different configurations when viewed from above, e.g., circular, rectangular, square, etc. The device 10 further comprise a channel region 13, a gate-all-around (GAA) gate structure 14, a bottom source/drain (S/D) region 16, a top S/D region 18, a bottom spacer 15B and a top spacer 15T. Also depicted is an illustrative bottom contact 20 that is conductively coupled to the bottom S/D region 16 and a top contact 22 that is conductively coupled to the top S/D region 18. In the depicted example, the gate structure 14 comprises a gate insulation layer 14A and a conductive gate electrode 14B. The materials of construction for the components of the device 10 may vary depending upon the particular application.
For many early device technology generations, the gate electrode structures of most transistor elements has comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed.
FIGS. 1B-1F simplistically depict one illustrative prior art process flow that is employed to form replacement gate structures on vertical transistor devices. FIG. 1B depicts the device 10 after several process operations were performed. First, a plurality of the above-described vertically oriented channel semiconductor structures 12A are formed above the substrate 12. Thereafter, several layers of material were sequentially deposited above the substrate: a layer of spacer material for the bottom spacer 15B, a sacrificial layer of material 21 (e.g., silicon dioxide) and a layer of spacer material for the top spacer 15T. Also depicted in FIG. 1B is a patterned etch mask layer 23. The patterned etch mask 23 may be made of a variety of different materials, e.g., photoresist, a combination of layers, etc.
FIG. 1C depicts the device 10 after an etching process was performed through the patterned etch mask 23 to remove the exposed portions of the top spacer layer 15T. The etching process stops on the sacrificial layer 21. FIG. 1C depicts the device after the patterned etch mask 23 was removed.
FIG. 1D depicts the device after a wet etching process was performed to remove the sacrificial layer 21 relative to the surrounding materials so as to define a plurality of replacement gate cavities 25.
FIG. 1E depicts the device 10 after simplistically depicted materials 14 for the replacement gate structure were formed so as to overfill the replacement gate cavities 25. The materials 14 for the replacement gate structure would normally include a high-k gate insulation layer (not separately shown), one or more additional metal-containing layers (e.g., work function adjusting metal layers), such as titanium nitride, and a bulk conductive fill material, such as tungsten or polysilicon. The high-k insulation layer and the additional metal-containing layers are typically formed by performing a conformal deposition process.
FIG. 1F depicts the device 10 after several process operations were performed. First, a chemical mechanical planarization (CMP) process was performed to planarize the upper surface of the gate materials 14 with the upper surface 15S of the patterned top spacer layer 15T. Thereafter, one or more anisotropic etching processes were performed to remove exposed portions of the gate materials 14, wherein the etching process ultimately stops on the layer of bottom spacer material 15B. As depicted, these operations result in the formation of separate GAA gate structures 14 that wrap around the channel portion 13 of the devices. Importantly, using this prior art process flow, the gate structures 14 are not self-aligned in that the lateral width 14L of the gate structure 14 is approximately defined by the lateral width 15L of the patterned features of the top spacer layer 15T. Since these features are defined by a patterning process, e.g., masking and etching, the control of the exact size and exact positioning of these patterned features is subject to the problems generally encountered when defining features using patterning processes such as, for example, positional accuracy relative to other structures (like the structures 12A), pattern transfer variations, etc. These types of issues are only expected to be more problematic as device dimensions continue to decrease with advancing technology.
The present disclosure is directed to methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts that may solve or reduce one or more of the problems identified above.